Producing a high performance and/or low consumption MOS transistor involves reducing the access resistance of that transistor as much as possible, i.e. the electrical resistance from the electric contacts connected to the source and the drain of the transistor until the channel of the transistor, in order to increase the current delivered by the transistor, and therefore improve the performance thereof.
The access resistance of a transistor is made up of three components:                the resistance of the extension regions, i.e. regions situated on the lateral sides of the channel and that are in electric contact with the source and the drain,        the resistance of the source and the drain,        the resistance of the electric contacts connected to the source and the drain of the transistor.        
To reduce the resistance of the extension regions, it is known to produce these extension regions from an alloy of metal and doped semiconductor, called silicide when the semiconductor forming the channel of the transistor is silicon-based. The penetration of that alloy in the semiconductor portion is very sensitive to the dispersion of the initial thickness of the semiconductor layer from which the channel is realized, which causes strong dispersions on the characteristics of the transistor. In order to improve the control of the penetration of the alloy under the spacers that are formed against the lateral sides of the transistor gate, above the channel, i.e. to improve the segregation of the dopants closest to the channel, it may be wise to etch the semiconductor intended to form the channel directly above the spacers and to realize a lateral siliconizing of the semiconductor which is therefore independent of the thickness of the semiconductor layer.
In order to reduce the access resistance of the transistor, it is also known to realize the source and the drain of the transistor from a metallic material.
Document EP 1 788 635 B1 describes the realization of a dual-gates MOS transistor with metallic source and drain. In the method described by this document, the channel is etched directly above the spacers and extension regions of the channel are implanted by dopants, then siliconized. Cavities are realized on the sides of the gate-channel structure by the deposition and planarization of one or several dielectric materials, then a lithography and an etching of those materials. A metal is then deposited on the whole of the structure, thereby filling the cavities. This metal is then planarized with stop on the hard mask having been used to produce the gate, thereby eliminating the metal region electrically connecting the source and the drain which are formed by the portions of metal arranged in the cavities.
This method has several drawbacks:                it is not possible to perform a siliconization of the gate,        the hard mask used to form the gate is also the stop layer of at least one chemical-mechanical polishing done in the active region of the transistor,        the control of this planarization must be perfect, in particular at the active region-isolation region (the active region corresponding to the region of the transistor where the channel, source and drain are situated, and the isolation region corresponding to the rest of the transistor) transition path because the risk of short circuit is significant if metallic portions persist after the planarization, in particular due to the fact that the gate-channel structure at the active region is thicker than the stack of materials found at the isolation region of the channel.        
Document WO 01/95383 A1 describes a method for producing transistors with metallic source and drain in which, after lateral siliconization of the sides of the channels, a metal is deposited over the entire surface of the wafer to make it possible to later take back the electric contacts of the source and drain. At this moment in the production method, all of the transistors are in internal short circuit (source-drain electric contact via the metal passing above the gate) and in short circuit with each other (via the metal passing above the isolation regions).
To eliminate the various short circuits (source-drain and inter-transistors), a chemical-mechanical planarization (CMP) is done with stop on the hard mask of the gate, then lithography and etching steps are done to eliminate short circuits between the transistors.
This approach has the following drawbacks in particular:                if the etching is done after the CMP, this requires significant selectivity of etching of the metal in relation to the present materials, for example relative to the hard mask of the SiO2 and/or Si3N4-based gate. It is consequently not possible to perform the etching from chlorinated and/or fluorinated solutions,        if the etching is done before the CMP, the thickness of metal to be etched is not consistent over the entire wafer. It is in particular more significant at the active region-isolation region transition paths, which causes the formation of metal spacers around the paths, and in particular around the gate material found in the isolation region, forming a short circuit between the source and the drain.        